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k4m28323ph - f(h)e/g/c/f october 2005 1 mobile sdram ? 1.8v power supply. ? lvcmos compatible with multiplexed address. ? four banks operation. ? mrs cycle with address key programs. -. cas latency (1, 2 & 3). -. burst length (1, 2, 4, 8 & full page). -. burst type (sequential & interleave). ? emrs cycle with address key programs. ? all inputs are sampled at the positive going edge of the system clock. ? burst read single-bit write operation. ? special function support. -. pasr (partial array self refresh). -. internal tcsr (temperature compensated self refresh) -. ds (driver strength) -. dpd (deep power down) ? dqm for masking. ? auto refresh. ? 64ms refresh period (4k cycle). ? commercial temperature operation (-25 c ~ 70 c). ? extended temperature operation (-25 c ~ 85 c). ? 90balls fbga ( -fxxx -pb, -hxxx -pb free). features the k4m28323ph is 134,217,728 bits synchronous high data rate dynamic ram organized as 4 x 1,048,576 words by 32 bits, fabricated with samsung?s high performance cmos technol- ogy. synchronous design allows pr ecise cycle control with the use of system clock and i/o trans actions are pos sible on every clock cycle. range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high per- formance memory system applications. general description ordering information - f(h)e/g : normal / low power, extended temperature(-25 c ~ 85 c) - f(h)c/f : normal / low power, commercial temperature(-25 c ~ 70 c) notes : 1. in case of 40mhz frequency, cl1 can be supported. part no. max freq. interface package k4m28323ph-f(h)e/g/c/f75 133mhz(cl3), 83mhz(cl2) lvcmos 90 fbga pb (pb free) k4m28323ph-f(h)e/g/c/f90 111mhz(cl3), 83mhz(cl2) k4m28323ph-f(h)e/g/c/f1l 111mhz(cl3) *1 , 66mhz(cl2) 1m x 32bit x 4 banks mobile sdram in 90fbga address configuration organization bank row column address 4m x 32 ba0, ba1 a0 - a11 a0 - a7 information in this document is provided in relation to samsung products, and is subjec t to change without notice. nothing in this document shall be const rued as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung product s or technology. all informatio n in this document is pro- vided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, crit ical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro- visions may apply.
k4m28323ph - f(h)e/g/c/f october 2005 2 mobile sdram bank select data input register 1m x 32 1m x 32 sense amp output buffer i/o control column decoder latency & burst length programming register address register row buffer refresh counter row decoder col. buffer lras lcbr lcke lras lcbr lwe ldqm clk cke cs ras cas we dqm lwe ldqm dqi clk add lcas lwcbr 1m x 32 1m x 32 timing register functional block diagram
k4m28323ph - f(h)e/g/c/f october 2005 3 mobile sdram 90ball(6x15) fbga 123789 a dq26 dq24 v ss v dd dq23 dq21 bdq28v ddq v ssq v ddq v ssq dq19 cv ssq dq27 dq25 dq22 dq20 v ddq dv ssq dq29 dq30 dq17 dq18 v ddq ev ddq dq31 nc nc dq16 v ssq fv ss dqm3 a3 a2 dqm2 v dd g a4 a5 a6 a10 a0 a1 h a7 a8 nc nc ba1 a11 j clk cke a9 ba0 cs ras kdqm1 nc nc cas we dqm0 lv ddq dq8 v ss v dd dq7 v ssq mv ssq dq10 dq9 dq6 dq5 v ddq nv ssq dq12 dq14 dq1 dq3 v ddq pdq11v ddq v ssq v ddq v ssq dq4 r dq13 dq15 v ss v dd dq0 dq2 pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 11 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable dqm 0 ~ dqm 3 data input/output mask dq 0 ~ 31 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground package dimension and pin configuration < bottom view *1 > < top view *2 > < top view *2 > symbol min typ max a- -1.00 a 1 0.25 - - e 7.90 8.00 8.10 e 1 - 6.40 - d 12.90 13.00 13.10 d 1 - 11.20 - e - 0.80 - b 0.45 0.50 0.55 z--0.10 [unit:mm] 521 63 4 8 97 f e d c b j h g a e d d 1 e 1 e z #a1 ball origin indicator m l k r p n k4m28323ph-xxxx samsung week a a1 b
k4m28323ph - f(h)e/g/c/f october 2005 4 mobile sdram dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 c ~ 85 c for extended, -25 c ~ 70 c for commercial) notes : 1. under all conditions, vddq must be less than or equal to vdd. 2. vih (max) = 2.2v ac.the overshoot voltage duration is 3ns. 3. vil (min) = -1.0v ac. the undershoot voltage duration is 3ns. 4. any input 0v vin vddq. input leakage currents include hi-z output leakag e for all bi-directional buffers with tri-state outputs. 5. dout is disabled, 0v vout vddq. parameter symbol min typ max unit note supply voltage v dd 1.7 1.8 1.95 v 1 v ddq 1.7 1.8 1.95 v 1 input logic high voltage v ih 0.8 x v ddq 1.8 v ddq + 0.3 v 2 input logic low voltage v il -0.3 0 0.3 v 3 output logic high voltage v oh v ddq -0.2 - - v i oh = -0.1ma output logic low voltage v ol - - 0.2 v i ol = 0.1ma input leakage current i li -2 - 2 ua 4 capacitance (v dd = 1.8v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 1.5 3.5 pf ras , cas , we , cs , cke, dqm c in 1.5 3.0 pf address c add 1.5 3.0 pf dq 0 ~ dq 31 c out 2.0 4.5 pf absolute maximum ratings notes: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 2.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 2.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma
k4m28323ph - f(h)e/g/c/f october 2005 5 mobile sdram dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 c ~ 85 c for extended, -25 c ~ 70 c for commercial) notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. internal tcsr can be supported. in comercial temp : 45 c/max 70 c. in extended temp : 45 c/max 85 c. 4. it has +/-5 c tolerance. 5. k4m28323ph-s(d)e/c** 6. k4m28323ph-s(d)g/f** 7.dpd(deep power down) function is an optional feature and it will be enabled upon request. please contact samsung for more information. 7. unless otherwise noted, input swing ievei is cmos(vih /vil=vddq/vssq). parameter symbol test condition version unit note -75 -90 -1l operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0 ma 45 40 40 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 0.3 ma i cc2 ps cke & clk v il (max), t cc = 0.3 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 10 ma i cc2 ns cke v ih (min), clk v il (max), t cc = input signals are stable 1 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 5 ma i cc3 ps cke & clk v il (max), t cc = 2 active standby current in non power-down mode (one bank active) i cc3 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 20 ma i cc3 ns cke v ih (min), clk v il (max), t cc = input signals are stable 10 ma operating current (burst mode) i cc 4 i o = 0 ma page burst 4banks activated t ccd = 2clks 60 50 50 ma 1 refresh current i cc 5 t arfc t arfc (min) 100 95 95 ma 2 self refresh current i cc 6 cke 0.2v internal tcsr 45 *4 85/70 c 3 -e/c full array 150 250 ua 5 1/2 of full 140 210 1/4 of full 135 190 -g/f full array 100 200 6 1/2 of full 90 160 1/4 of full 85 140 deep power down current i cc 8 cke 0.2v 10 ua 7
k4m28323ph - f(h)e/g/c/f october 2005 6 mobile sdram 1.8v 13.9k ? 10.6k ? output 20pf voh (dc) = vddq - 0.2v, ioh = -0.1ma vol (dc) = 0.2v, iol = 0.1ma vtt=0.5 x vddq 50 ? output 20pf z0=50 ? figure 2. ac output load circuit figure 1. dc output load circuit ac operating test conditions (v dd = 1.7v 1.95v, t a = -25 ~ 85 c for extended, -25 ~ 70 c for commercial) parameter value unit ac input levels (vih/vil) 0.9 x v ddq / 0.2 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see figure 2
k4m28323ph - f(h)e/g/c/f october 2005 7 mobile sdram operating ac parameter (ac operating conditions unless otherwise noted) notes: 1. the minimum number of clock cycles is determined by dividi ng the minimum time required with clock cycle time and then roundi ng off to the next higher integer. 2. minimum delay is required to complete write. 3. maximum burst refresh cycle : 8 4. all parts allow every cycle column address change. 5. in case of row precharge interrupt, auto precharge and read burst stop. parameter symbol version unit note -75 -90 -1l row active to row active delay t rrd (min) 15 18 18 ns 1 ras to cas delay t rcd (min) 22.5 24 27 ns 1 row precharge time t rp (min) 22.5 24 27 ns 1 row active time t ras (min) 50 50 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 72.5 74 77 ns 1 last data in to row precharge t rdl (min) 15 ns 2 last data in to active delay t dal (min) trdl + trp - last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 auto refresh cycle time t arfc (min) 80 ns 3 exit self refresh to active command t srfx (min) 120 ns col. address to col. address delay t ccd (min) 1 clk 4 number of valid output data cas latency=3 2 ea 5 number of valid output data cas latency=2 1 number of valid output data cas latency=1 - 0
k4m28323ph - f(h)e/g/c/f october 2005 8 mobile sdram ac characteristics (ac operating conditions unless otherwise noted) notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, trans ient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. parameter symbol -75 -90 -1l unit note min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 9 1000 9 1000 ns 1 cas latency=2 t cc 12 12 15 cas latency=1 t cc - - 25 clk to valid output delay cas latency=3 t sac 6 7 7 ns 1,2 cas latency=2 t sac 9 9 10 cas latency=1 t sac - - 20 output data hold time cas latency=3 t oh 2.5 2.5 2.5 ns 2 cas latency=2 t oh 2.5 2.5 2.5 cas latency=1 t oh - - 2.5 clk high pulse width t ch 2.5 3.0 3.0 ns 3 clk low pulse width t cl 2.5 3.0 3.0 ns 3 input setup time t ss 2.0 2.0 2.0 ns 3 input hold time t sh 1 1 1 ns 3 clk to output in low-z t slz 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 6 7 7 ns cas latency=2 9 9 10 cas latency=1 - - 20
k4m28323ph - f(h)e/g/c/f october 2005 9 mobile sdram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a11 & ba0 ~ ba1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are the same as cbr refresh of dram. the automatical precharge without ro w precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. partial self refresh can be issued only after setting partial self refresh mode of emrs. 4. ba0 ~ ba1 : bank select addresses. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data- in at that same clk in writ e operation (write dqm latency is 0), but in read operation, it makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm ba 0,1 a10/ap a11, a9 ~ a0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a0~a7) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a0~a7) 4 auto precharge enable h 4, 5 deep power down entry h l l h h l x x exit l h h x x x x burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h
k4m28323ph - f(h)e/g/c/f october 2005 10 mobile sdram register programmed with extended mrs address ba1 ba0 a11 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function mode select rfu *1 ds rfu *1 pasr normal mrs mode test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 1 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 0 0 setting for nor- mal mrs 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page reserved register programmed with normal mrs address ba0 ~ ba1 a11 ~ a10/ap a9 *2 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu w.b.l test mode cas latency bt burst length a. mode register field table to program modes notes: 1. rfu(reserved for future use) should stay "0" during mrs cycle. 2. if a9 is high during mrs cycle, "burst r ead single bit write" function will be enabled. mode select driver strength pasr ba1 ba0 mode a6 a5 driver strength a2 a1 a0 size of refreshed array 0 0 normal mrs 0 0 full 0 0 0 full array 0 1 reserved 0 1 1/2 0 0 1 1/2 of full array 1 0 emrs for mobile sdram 1 0 1/4 0 1 0 1/4 of full array 1 1 reserved 1 1 1/8 0 1 1 reserved reserved address 1 0 0 reserved a11~a10/ap a9 a8 a7 a4 a3 1 0 1 reserved 0 0 0 0 0 0 1 1 0 reserved 1 1 1 reserved emrs for pasr(partial array self ref.) & ds(driver strength)
k4m28323ph - f(h)e/g/c/f october 2005 11 mobile sdram 1. in order to save power consumpt ion, mobile sdram has pasr option. 2. mobile sdram supports 3 kinds of pasr in self refr esh mode : full array, 1/2 of full array, 1/4 of full array. ba1=0 partial self refresh area 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command to define ds or pasr operating type of the device after normal mrs. for operating with ds or pasr , set ds or pasr mode in emrs setting stage. in order to adjust another mode in the state of ds or pasr mode, additional emrs set is requir ed but power up sequence is not needed again at this time. in that case, all banks have to be in idle state prior to adjusting emrs set. ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=1 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 partial array self refresh b. power up sequence internal temperature compensated self refresh (tcsr) - full array - 1/2 array - 1/4 array note : 1. in order to save power consumption, m obile-sdram includes the interna l temperature sensor and contr ol units to control the self refresh cycle automatically a ccording to the two temperature range ; 45 c and 85 c(for extended) / 70 c(for commercial). 2. if the emrs for external tcsr is issued by the controller, this emrs c ode for tcsr is ignored. 3. it has +/- 5 c tolerance. temperature range self refresh current (idd6) unit - e / c - g / f full array 1/2 array 1/4 array full array 1/2 array 1/4 array 45 c *3 150 140 135 100 90 85 ua 85/70 c 250 210 190 200 160 140
k4m28323ph - f(h)e/g/c/f october 2005 12 mobile sdram c. burst sequence 1. burst length = 4 initial address sequential interleave a1 a0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. burst length = 8 initial address sequential interleave a2 a1 a0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
dram product search related document related link copyright? 2007 samsung. all righ t http://www.samsung.com/ privacy legal sitemap contact us search parametric search ordering information part no. search - device operations & ti m diagram for 1.8v device operations &tim i diagram for 2.5/3.3v dram application notes label & code information packing information package information memory brochures sdr package & packing production & availability sdr > k4m28323ph technical file download package & packing production & availability rohs information part number K4M28323PH-HG1L0 k4m28323ph-hg750 k4m28323ph-w3000 package type fbga fbga wafer packing tray tray jar pins 90 90 package size 8.0x13.0 8.0x13.0 marking code k4m28323ph-hg1l k4m28323p h-hg75 k4m28323ph-w300 compliance with rohs lead free lead free lead free home > products > dram > mobile sdram > mobile sdr sdram ddr3 sdram ddr2 sdram ddr sdram sdram mobile sdram mobile sdr sdram mobile ddr sdram eol products xdr ? dram rdram? graphics memory utram(psram) consumer dram pa g e 1 of 3 samsung semiconductor - p roducts - dram - mobile sdram 07-se p -2007 mhtml:file://y:\avnet\09082007\ sams\k4m28323ph-w3000ry.mht
technical file download rohs information part number k4m28323ph- hg1l0 k4m28323ph- hg750 k4m28323ph- w3000 life cycle production production production die revision mass production mass production mass production moq (small box) 1120 1120 0 moq (large box) 4480 4480 0 qual sample q2/2005 q2/2005 q2/2005 mass production q3/2005 q3/2005 q3/2005 last time buy n/a n/a n/a last time ship n/a n/a n/a replacement part number - specification data file rev # size updated date data sheet 145kb 2007/08/13 - simulation models file rev # size updated date ibis ibis : 3.2, file : 1.0 264kb 2007/08/13 readme 1kb 2007/08/13 verilog 90kb 2007/08/13 for more information, please click the button next to the product name. pa g e 2 of 3 samsung semiconductor - p roducts - dram - mobile sdram 07-se p -2007 mhtml:file://y:\avnet\09082007\ sams\k4m28323ph-w3000ry.mht
material declaration sheet does not contain hazardous materials defined in china rohs declaration letter contains hazardous materials defined in china rohs K4M28323PH-HG1L0 is lead-free and rohs-compliant. k4m28323ph-hg750 is lead-free and rohs-compliant. k4m28323ph-w3000 is lead-free and rohs-compliant. pa g e 3 of 3 samsung semiconductor - p roducts - dram - mobile sdram 07-se p -2007 mhtml:file://y:\avnet\09082007\ sams\k4m28323ph-w3000ry.mht

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